New approach to size selection and thin film growth of silicon quantum dots and applications

Project Details


The intact sublimation of silicon nanocrystals is an extremely novel and unexpected observation. I have used this method to deposit silicon nanocrystals on a variety of substrates placed in the resulted vapour (sapphire plates, graphite sheet, silicon wafer and gold nitride films). The ability to evaporate and deposit nanocrystals in high vacuum may be useful for the size-controlled preparation of new nanoscale quantum-confined structures. Many of the potential uses of nanoparticles demand that the particles have well defined sizes. But this is not easy to achieve at such small scales, and it has previously been largely a matter of trial and error. This novel intact sublimation of silicon nanocrystals could provide a novel method for size selection and thin film preparation. One example of applications is replacing the conventional oxide layer in floating gate memory devices with a layer of nanocrystals. Currently, nonvolatile memory devices utilize floating gate field-effect transistor technology to store information, and these have many applications e.g. mobile phones, digital cameras, camcorders, MP3 players, digital games, iPods, flash cards and removable storage devices, which is in a rapidly growing market ($40 billion in 2007, up 12.9% from 2006). In such memory devices, charge is stored on a silicon floating gate that is separated from the substrate by a dielectric tunneling barrier. Typically, the tunneling barrier consists of a thin thermally-grown SiO2 layer. This tunneling barrier controls the retention time and the program/erase speed of the device. When a ''program'' bias is applied to the device, charge tunnels through the barrier and remains stored on the floating gate after the program voltage is removed. Firstly, since the tunneling barrier must be able to inject a current during programming and to retain charge, a compromise must be made when designing memory devices that integrate a tunneling barrier. When the barrier is made relatively thick, long charge retention times are achieved, but a higher voltage (and a longer time) is required to program and erase the floating gate. When the barrier is thin, the programming and erase process will be more rapid, but increased charge leakage will reduce the retention time. If a monolayer comprised of silicon nanocrystals (aka quantum dots) was to replace the SiO2 layer, an effective lowering of the barrier would be observed. This barrier lowering effect will allow an increase in the tunnel current density and a subsequent increase in the floating gate program/erase speed. Secondly, for a normal flash memory, a major problem is caused by the non-uniformity of the oxide; if there is a weak spot where the leakage current density is larger, it acts as a sink and all stored charges in the floating gate would leak away through it. This problem increases with the thinning of the oxide layer. Again, if the floating gate is replaced with nanoparticles the "weak spot" will only affect a small number of nanoparticles and has no effect on the charge stored in other particles. Therefore, in this design, the thickness of both tunneling barrier oxide and inter-level oxide can be reduced without sacrificing the memory retention time. Thirdly, since the shift in the device's threshold depends on the particle size, a wide size distribution would wash out the operating threshold. Thus the size selection is a big issue for this application. This research project is the first such research in Europe and is an opportunity for UK to enter this major area of nanocrystals based memory devices.
In the research program described here we will study the dynamics of the evaporation-deposition process of nanocrystals in vacuum, which will contribute to the development of the novel method for nanocrystals selection by size. This novel method will be developed further for forming size-controlled nanocrystal thin films, which could be used to replace the SiO2 layer in floating gate memory devices.
Effective start/end date26/05/0925/07/12


  • Engineering and Physical Sciences Research Council: £316,864.00