Automated technique for high-level circuit synthesis from temporal logic specifications

R. D. Dowsing, R. Elliott, I. Marshall

Research output: Contribution to journalArticlepeer-review


A general-purpose strategy for the synthesis of digital circuits from high-level behavioural specifications expressed in the temporal-logic language Tempura is described. This strategy has been implemented as a synthesis tool called AST, and the application of AST to part of the specification for an error-encoder circuit is examined
Original languageEnglish
Pages (from-to)145-152
Number of pages8
JournalIEE Proceedings: Computers and Digital Techniques
Issue number3
Publication statusPublished - 1994

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