Automated technique for high-level circuit synthesis from temporal logic specifications

R. D. Dowsing; R. Elliott; I. Marshall

doi:10.1049/ip-cdt:19941005

Automated technique for high-level circuit synthesis from temporal logic specifications

R. D. Dowsing
, R. Elliott
, I. Marshall

School of Computing Sciences

Research output: Contribution to journal › Article › peer-review

Abstract

A general-purpose strategy for the synthesis of digital circuits from high-level behavioural specifications expressed in the temporal-logic language Tempura is described. This strategy has been implemented as a synthesis tool called AST, and the application of AST to part of the specification for an error-encoder circuit is examined

Original language	English
Pages (from-to)	145-152
Number of pages	8
Journal	IEE Proceedings: Computers and Digital Techniques
Volume	141
Issue number	3
DOIs	https://doi.org/10.1049/ip-cdt:19941005
Publication status	Published - 1994

Access to Document

10.1049/ip-cdt:19941005

Cite this

@article{b097492a0b4b40e4a6bb92295c71db05,

title = "Automated technique for high-level circuit synthesis from temporal logic specifications",

abstract = "A general-purpose strategy for the synthesis of digital circuits from high-level behavioural specifications expressed in the temporal-logic language Tempura is described. This strategy has been implemented as a synthesis tool called AST, and the application of AST to part of the specification for an error-encoder circuit is examined",

author = "Dowsing, \{R. D.\} and R. Elliott and I. Marshall",

year = "1994",

doi = "10.1049/ip-cdt:19941005",

language = "English",

volume = "141",

pages = "145--152",

journal = "IEE Proceedings: Computers and Digital Techniques",

issn = "1350-2387",

publisher = "Institution of Engineering and Technology",

number = "3",

}

TY - JOUR

T1 - Automated technique for high-level circuit synthesis from temporal logic specifications

AU - Dowsing, R. D.

AU - Elliott, R.

AU - Marshall, I.

PY - 1994

Y1 - 1994

N2 - A general-purpose strategy for the synthesis of digital circuits from high-level behavioural specifications expressed in the temporal-logic language Tempura is described. This strategy has been implemented as a synthesis tool called AST, and the application of AST to part of the specification for an error-encoder circuit is examined

AB - A general-purpose strategy for the synthesis of digital circuits from high-level behavioural specifications expressed in the temporal-logic language Tempura is described. This strategy has been implemented as a synthesis tool called AST, and the application of AST to part of the specification for an error-encoder circuit is examined

U2 - 10.1049/ip-cdt:19941005

DO - 10.1049/ip-cdt:19941005

M3 - Article

SN - 1350-2387

VL - 141

SP - 145

EP - 152

JO - IEE Proceedings: Computers and Digital Techniques

JF - IEE Proceedings: Computers and Digital Techniques

IS - 3

ER -