Industrial experience with test generation languages for processor verification

Michael Behm; John Ludden; Yossi Lichtenstein; Michal Rimon; Michael Vinov

doi:10.1145/996566.996578

Industrial experience with test generation languages for processor verification

Michael Behm, John Ludden, Yossi Lichtenstein, Michal Rimon, Michael Vinov

Norwich Business School

Research output: Contribution to conference › Paper › peer-review

36 Citations (Scopus)

Abstract

We report on our experience with a new test generation language for processor verification. The verification of two superscalar multiprocessors is described and we show the ease of expressing complex verification tasks. The cost and benefit are demonstrated: training takes up to six months; the simulation time required for a desired level of coverage has decreased by a factor of twenty; the number of escape bugs has been reduced.

Original language	English
Pages	36-40
Number of pages	5
DOIs	https://doi.org/10.1145/996566.996578
Publication status	Published - Jun 2004
Event	41st Annual Design Automation Conference - Duration: 1 Jun 2004 → …

Conference

Conference	41st Annual Design Automation Conference
Period	1/06/04 → …

Keywords

processor verification
test generation
functional verification

Access to Document

10.1145/996566.996578

http://doi.acm.org/10.1145/996566.996578

Cite this

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title = "Industrial experience with test generation languages for processor verification",

abstract = "We report on our experience with a new test generation language for processor verification. The verification of two superscalar multiprocessors is described and we show the ease of expressing complex verification tasks. The cost and benefit are demonstrated: training takes up to six months; the simulation time required for a desired level of coverage has decreased by a factor of twenty; the number of escape bugs has been reduced.",

keywords = "processor verification, test generation, functional verification",

author = "Michael Behm and John Ludden and Yossi Lichtenstein and Michal Rimon and Michael Vinov",

note = "Nominated for best paper award; 41st Annual Design Automation Conference ; Conference date: 01-06-2004",

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AU - Ludden, John

AU - Lichtenstein, Yossi

AU - Rimon, Michal

AU - Vinov, Michael

N1 - Nominated for best paper award

PY - 2004/6

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AB - We report on our experience with a new test generation language for processor verification. The verification of two superscalar multiprocessors is described and we show the ease of expressing complex verification tasks. The cost and benefit are demonstrated: training takes up to six months; the simulation time required for a desired level of coverage has decreased by a factor of twenty; the number of escape bugs has been reduced.

KW - processor verification

KW - test generation

KW - functional verification

U2 - 10.1145/996566.996578

DO - 10.1145/996566.996578

M3 - Paper

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EP - 40

T2 - 41st Annual Design Automation Conference

Y2 - 1 June 2004

ER -