Industrial experience with test generation languages for processor verification

Michael Behm, John Ludden, Yossi Lichtenstein, Michal Rimon, Michael Vinov

Research output: Contribution to conferencePaperpeer-review

35 Citations (Scopus)

Abstract

We report on our experience with a new test generation language for processor verification. The verification of two superscalar multiprocessors is described and we show the ease of expressing complex verification tasks. The cost and benefit are demonstrated: training takes up to six months; the simulation time required for a desired level of coverage has decreased by a factor of twenty; the number of escape bugs has been reduced.
Original languageEnglish
Pages36-40
Number of pages5
Publication statusPublished - Jun 2004
EventProceedings of the 41st annual Design Automation Conference -
Duration: 1 Jun 2004 → …

Conference

ConferenceProceedings of the 41st annual Design Automation Conference
Period1/06/04 → …

Keywords

  • processor verification
  • test generation
  • functional verification

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