Test program generation for functional verification of PowerPC processors in IBM

Aharon Aharon, Dave Goodman, Moshe Levinger, Yossi Lichtenstein, Yossi Malka, Charlotte Metzger, Moshe Molcho, Gil Shurek

Research output: Contribution to conferencePaperpeer-review

132 Citations (Scopus)


A new methodology and test program generator have been used for the functional verification of six IBM PowerPC processors. The generator contains a formal model of the PowerPC architecture and a heuristic data-base of testing expertise. It has been used on daily basis for two years by about a hundred designers and testing engineers in four IBM sites. The new methodology reduced significantly the functional verification period and time to market of the PowerPC processors. Despite the complexity of the PowerPC architecture, the three processors verified so far had fully functional first silicon. 1 Introduction A new methodology and tool for functional test program generation has been used for several IBM PowerPC processors. The functional verification period and the processors time to market were reduced. Only one fifth of the simulation cycles needed to verify a RISC System/6000 processor with a previous generator was needed with the new methodology for a PowerPC processor. The new g...
Original languageEnglish
Number of pages7
Publication statusPublished - Jun 1995
Event32nd Annual ACM/IEEE Design Automation Conference - San Francisco, United States
Duration: 12 Jun 199516 Jun 1995


Conference32nd Annual ACM/IEEE Design Automation Conference
Abbreviated titleDAC95
Country/TerritoryUnited States
CitySan Francisco

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