Test program generation for functional verification of PowerPC processors in IBM

Aharon Aharon; Dave Goodman; Moshe Levinger; Yossi Lichtenstein; Yossi Malka; Charlotte Metzger; Moshe Molcho; Gil Shurek

doi:10.1145/217474.217542

Test program generation for functional verification of PowerPC processors in IBM

Aharon Aharon, Dave Goodman, Moshe Levinger, Yossi Lichtenstein, Yossi Malka, Charlotte Metzger, Moshe Molcho, Gil Shurek

Norwich Business School

Research output: Contribution to conference › Paper › peer-review

128 Citations (Scopus)

Abstract

A new methodology and test program generator have been used for the functional verification of six IBM PowerPC processors. The generator contains a formal model of the PowerPC architecture and a heuristic data-base of testing expertise. It has been used on daily basis for two years by about a hundred designers and testing engineers in four IBM sites. The new methodology reduced significantly the functional verification period and time to market of the PowerPC processors. Despite the complexity of the PowerPC architecture, the three processors verified so far had fully functional first silicon. 1 Introduction A new methodology and tool for functional test program generation has been used for several IBM PowerPC processors. The functional verification period and the processors time to market were reduced. Only one fifth of the simulation cycles needed to verify a RISC System/6000 processor with a previous generator was needed with the new methodology for a PowerPC processor. The new g...

Original language	English
Pages	279-285
Number of pages	7
DOIs	https://doi.org/10.1145/217474.217542
Publication status	Published - Jun 1995
Event	32nd Annual ACM/IEEE Design Automation Conference - San Francisco, United States Duration: 12 Jun 1995 → 16 Jun 1995

Conference

Conference	32nd Annual ACM/IEEE Design Automation Conference
Abbreviated title	DAC95
Country/Territory	United States
City	San Francisco
Period	12/06/95 → 16/06/95

Access to Document

10.1145/217474.217542

Cite this

@conference{8e4c682ddbaf43328df65361bf19a0e0,

title = "Test program generation for functional verification of PowerPC processors in IBM",

abstract = "A new methodology and test program generator have been used for the functional verification of six IBM PowerPC processors. The generator contains a formal model of the PowerPC architecture and a heuristic data-base of testing expertise. It has been used on daily basis for two years by about a hundred designers and testing engineers in four IBM sites. The new methodology reduced significantly the functional verification period and time to market of the PowerPC processors. Despite the complexity of the PowerPC architecture, the three processors verified so far had fully functional first silicon. 1 Introduction A new methodology and tool for functional test program generation has been used for several IBM PowerPC processors. The functional verification period and the processors time to market were reduced. Only one fifth of the simulation cycles needed to verify a RISC System/6000 processor with a previous generator was needed with the new methodology for a PowerPC processor. The new g...",

author = "Aharon Aharon and Dave Goodman and Moshe Levinger and Yossi Lichtenstein and Yossi Malka and Charlotte Metzger and Moshe Molcho and Gil Shurek",

year = "1995",

month = jun,

doi = "10.1145/217474.217542",

language = "English",

pages = "279--285",

note = "32nd Annual ACM/IEEE Design Automation Conference, DAC95 ; Conference date: 12-06-1995 Through 16-06-1995",

}

Test program generation for functional verification of PowerPC processors in IBM. / Aharon, Aharon; Goodman, Dave; Levinger, Moshe; Lichtenstein, Yossi; Malka, Yossi; Metzger, Charlotte; Molcho, Moshe; Shurek, Gil.

1995. 279-285 Paper presented at 32nd Annual ACM/IEEE Design Automation Conference, San Francisco, California, United States.

Research output: Contribution to conference › Paper › peer-review

TY - CONF

T1 - Test program generation for functional verification of PowerPC processors in IBM

AU - Aharon, Aharon

AU - Goodman, Dave

AU - Levinger, Moshe

AU - Lichtenstein, Yossi

AU - Malka, Yossi

AU - Metzger, Charlotte

AU - Molcho, Moshe

AU - Shurek, Gil

PY - 1995/6

Y1 - 1995/6

N2 - A new methodology and test program generator have been used for the functional verification of six IBM PowerPC processors. The generator contains a formal model of the PowerPC architecture and a heuristic data-base of testing expertise. It has been used on daily basis for two years by about a hundred designers and testing engineers in four IBM sites. The new methodology reduced significantly the functional verification period and time to market of the PowerPC processors. Despite the complexity of the PowerPC architecture, the three processors verified so far had fully functional first silicon. 1 Introduction A new methodology and tool for functional test program generation has been used for several IBM PowerPC processors. The functional verification period and the processors time to market were reduced. Only one fifth of the simulation cycles needed to verify a RISC System/6000 processor with a previous generator was needed with the new methodology for a PowerPC processor. The new g...

AB - A new methodology and test program generator have been used for the functional verification of six IBM PowerPC processors. The generator contains a formal model of the PowerPC architecture and a heuristic data-base of testing expertise. It has been used on daily basis for two years by about a hundred designers and testing engineers in four IBM sites. The new methodology reduced significantly the functional verification period and time to market of the PowerPC processors. Despite the complexity of the PowerPC architecture, the three processors verified so far had fully functional first silicon. 1 Introduction A new methodology and tool for functional test program generation has been used for several IBM PowerPC processors. The functional verification period and the processors time to market were reduced. Only one fifth of the simulation cycles needed to verify a RISC System/6000 processor with a previous generator was needed with the new methodology for a PowerPC processor. The new g...

U2 - 10.1145/217474.217542

DO - 10.1145/217474.217542

M3 - Paper

SP - 279

EP - 285

T2 - 32nd Annual ACM/IEEE Design Automation Conference

Y2 - 12 June 1995 through 16 June 1995

ER -